Proposed Abstract:

In contemporary cryptographic systems, the secure generation of high-quality pseudo-random numbers is essential for ensuring the integrity and confidentiality of data, particularly in resource-constrained environments such as IOT devices, embedded systems, and sensor networks. Existing cryptographically secure pseudo-random number generators (CSPRNGs) that leverage algorithms like AES, DES, or SHA, although highly secure, often face challenges related to resource efficiency, power consumption, and complexity, making them less suitable for low-power and area-sensitive applications. This paper introduces a novelty 32-bit CSPRNG architecture that integrates the lightweight PRESENT block cipher with a dual polynomial-based pseudo-random number generator (PRNG) scheme. The proposed design employs two distinct polynomial PRNGs: one tailored for generating the plaintext input and the other for the key input to the PRESENT cipher. This dual-PRNG approach not only generates non-repetitive random patterns but also significantly enhances the precision and quality of randomness, providing a fortified layer of security against cryptanalytic attacks. The architecture is meticulously implemented in Verilog HDL and synthesized on the Xilinx Virtex-5 FPGA, a platform known for its balance of performance and efficiency. The proposed system is thoroughly evaluated against key performance metrics, including area utilization, critical path delay, and power consumption. Our results demonstrate that the novel combination of the PRESENT cipher with dual polynomial PRNGs offers a superior solution, reducing resource usage and power consumption while maintaining or exceeding the security standards provided by more complex algorithms like AES and SHA. Moreover, this work delves into the theoretical underpinnings of dual polynomial PRNGs, illustrating how their integration within the CSPRNG architecture not only mitigates the risks of pattern repetition but also increases the entropy and unpredictability of the generated numbers. This dual-PRNG strategy is shown to be particularly effective in applications requiring long-term operation without re-seeding, thus extending the operational life of secure systems in the field. In decision, the proposed CSPRNG architecture represents a significant advancement in the design of secure and efficient random number generators, tailored specifically for environments where both security and resource efficiency are paramount. The innovative use of dual polynomial PRNGs alongside the PRESENT cipher positions this work as a pivotal contribution to the field of cryptographic hardware design, with direct implications for the future development of secure, low-power systems in emerging technologies such as IOT, RFID, and other distributed network applications.

Software Implementation:

• Modelsim
• Xilinx

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Design and Implementation of 32-bit CSPRNG using the PRESENT cipher with Dual Polynomial PRNG for Enhanced Randomness and Precision