Proposed Title:

FPGA Implementation of Area Efficient Dual Quality Approximate Convolution Systolic Array Architecture

Improvement of this project :

• To design a Systolic Array based 128×128 Convolution Operation using 3×3 kernel size (convolution Filter)

• To design 8×8 Dual quality approximate multiplier and integrate into convolution method, and compared with exact multiplier based convolution method.

• Design done with Verilog HDL, and synthesized using Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.

Software Implementation:

• Modelsim
• Xilinx 

Proposed System:

This study introduces an FPGA implementation of a systolic array-based 128×128 convolution operation, leveraging a novel 8×8 dual quality approximate multiplier designed for image processing applications. The systolic array, configured with a 3×3 convolution kernel, utilizes the parallel processing capabilities of FPGAs to achieve high-throughput computation. The proposed 8×8 dual quality approximate multiplier provides a flexible approach to balancing computational accuracy and hardware efficiency. The complete design is described in Verilog HDL and synthesized using the Xilinx Virtex-5 FPGA platform. A comprehensive evaluation comparing the approximate multiplier-based convolution method with the traditional exact multiplier-based method is conducted, focusing on key performance metrics such as area, delay, and power consumption. Our results demonstrate that the dual quality approximate multiplier significantly reduces hardware resource utilization and power consumption. This work contributes to the development of efficient, compact, and adaptive hardware architectures for modern convolutional neural network (CNN) implementations.

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Design and Evaluation of Inexact Computation based Systolic Array for Convolution