Proposed Title :

FPGA Design of 4:2, 5:2, and 7:2 Compressor Used in Error-Resilient Approximate Multiplier for Error Compensation

Improvement of this project :

• To reduce the number of stage and logic sizes in the Error Compensation & Error Resilient Approximate Multiplier using 4:2, 5:2 and 7:2 Compressors.

• To design 8-bit and 16-bit Multiplier Architecture and synthesized in Xilinx Vertex-5 FPGA.

• Compared the existing architecture in the base paper and proved the performance.

• Implemented this Approximate Multiplier into Image Multiplication and proved the PSNR and SSIM Values.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

Approximate computing is a potential methodology for trading off precision for improved hardware precision in error-tolerant applications like neural networks and image processing. In this brief, a very effective approximate multiplier with error correction is demonstrated. The proposed multiplier treats the less important half of the result as a fixed compensating term. The second half is carefully computed to give an extremely efficient hardware-accuracy tradeoff. In addition, a simple but effective error compensation module (ECM) is introduced, which greatly improves accuracy. To decrease the number of partial product reduction stages and logic sizes in the approximate multiplier module, the proposed multiplier was constructed using 4:2, 5:2, and 7:2 compressors. To create an 8-bit and 16-bit multiplier architecture and compared the existing architecture and demonstrated its performance. This Approximate Multiplier was implemented into Image Multiplication and the PSNR and SSIM values were shown. Furthermore, the accuracy and efficacy of the proposed multiplier in neural networks and image multiplication are assessed using Modelsim and Xilinx simulations. According to the research results, the proposed multiplier has a high accuracy equivalent to the precise multiplier in Neural Networks and delivers an average PSNR and SSIM value in image multiplication. As a result, it may be a viable replacement for accurate multipliers in realistic error-tolerant applications.

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An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications