Proposed Title:

FPGA Implementation of 8^th Order ECG IIR Filter design using Array
Multiplier with XOR-MUX Full Adder Design

Improvement of this project :

• To design 8^th IIR Filter design for ECG applications.

• To design IIR Filter which using Chebyshev Type 2, Direct Form II design architecture.

• The Filter design compared using Exact and XOR-MUX based Full adder design with Array Multiplier and proved the performance analysis of Area, Delay and power.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

The goal of this research is to design and implement an 8th-order Infinite Impulse Response (IIR) digital filter on a Field Programmable Gate Array (FPGA) for real-time Electrocardiogram (ECG) signal processing. Efficient low-pass digital filtering is crucial in medical applications to ensure accurate heart rate monitoring and early detection of cardiac anomalies. This work focuses exclusively on the design of IIR filters using the Chebyshev Type II method, realized through a Direct Form II architecture. The filter is developed using Verilog HDL and synthesized on a Xilinx Spartan-6 FPGA using the Xilinx ISE Design Suite. To improve hardware efficiency, the architecture integrates an Array Multiplier along with an XOR-MUX based Full Adder, leading to notable reductions in area, power consumption, and computational delay. Performance analysis demonstrates that the proposed IIR filter design is highly optimized for low-power, real-time biomedical signal processing, making it a strong candidate for practical ECG monitoring systems.

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A Unified Approach for Realization of IIR Filters in Delta Domain