Proposed Title :

A Novel Method of Reversible Logic using Majority Logic Gate Full Adder and Compressor 4:2 for Wallace Tree Multiplier

Improvement of this project :

• To design a Majority Logic Gate using Reversible Technique with using Feynman and Toffoli Gate.

• To design a Reversible Majority Logic Gate Full Adder and Reversible Majority Logic Gate Compressor 4:2 and proved comparisons with Conventional Majority Logic Gate Full Adder and Conventional 4:2 Compressor.

• To design a 8×8 Reversible Majority Logic Wallace Tree Multiplier using Conventional and Reversible Method with 16-bit Ladner Fischer Parallel Prefix Adder.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

The latency of arithmetic adders and subsequently multipliers that are implemented as a succession of such Boolean operations grows significantly increases with bit-width and memory logic. In this study, we address the excessive latency by using the Wallace Tree multiplier architecture and enhancing the addition operation in each step of the Wallace Tree. This allows us to reduce the latency, memory logic and power significantly. Because this architecture was developed with majority logic gate using reversible technique, the majority logic primitive was used for the addition and 4:2 compressor to reduce number of partial product stage addition in Wallace Tree multiplier. In addition, a high degree of parallelism at the gate level is used at the array level by running several majority gates in each column of the array. In addition, the multiplier that has been presented may be implemented in a conventional transistor accessed memory array without the need for significant alterations to the peripheral circuitry of the array, and it uses a minimal amount of power. The proposed work of this paper to design a Majority Logic Gate  using Reversible Technique with using Feynman and Toffoli Gate. And design a Reversible Majority Logic Gate Full Adder and Reversible Majority Logic Gate Compressor 4:2 and proved comparisons with Conventional Majority Logic Gate Full Adder and Conventional 4:2 Compressor. Thus the final design of 8×8 Reversible Majority Logic Wallace Tree Multiplier using Conventional and Reversible Method with 16-bit Ladner Fischer Parallel Prefix Adder. Finally this work was developed using Verilog HDL and synthesized using Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.

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A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic