Proposed Title:

A Hybrid TRNG-PRNG Architecture for High-Performance and Resource-Efficient Random Number Generation on FPGA

Improvement of this project:

1. To design the 32-bit hybrid designs of TRNGs can seed a PRNG to combine the benefits of both systems: true randomness from the TRNG and fast generation from the PRNG.

2. To Compare the existing and proposed in 32-bit architecture, with performance analysis of LUT, Slice Registers, IOB, Delay and Power using Xilinx Vertex-5.

Proposed Abstract:

In this work, we propose a novel hybrid architecture that combines a True Random Number Generator (TRNG) with a Polynomial-based Pseudo-Random Number Generator (PRNG) to achieve high-quality randomness and high-speed random number generation. The 32-bit architecture leverages the unpredictability of the TRNG to periodically seed the PRNG, enhancing entropy and addressing the limitations of standalone systems. The design is implemented on a Xilinx Vertex-5 FPGA and optimized for resource efficiency, minimizing LUT, Slice Register, and IOB utilization. Performance analysis reveals improvements in delay, power consumption, and throughput while ensuring compliance with randomness standards through NIST SP 800-22 and Diehard tests. This hybrid approach offers a scalable and secure solution for cryptographic and embedded system applications.

Software Implementation:

• Modelsim
• Xilinx

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A Hybrid TRNG-PRNG Architecture for High-Performance and Resource-Efficient Random Number Generation on FPGA