Peak Cancellation Method With IIR Filters and Its FPGA Implementation
Peak Cancellation Method With IIR Filters
and Its FPGA Implementation
Abstract:
To improve the efficiency of power amplifiers (PA) in communication transmitters, peak cancellation (PC) in the time domain is often implemented on a Field-programmable gate array (FPGA) to reduce the peak-to-average power ratio (PAPR) of the baseband signals. However, to reduce the out-of-band radiation, the existing techniques tend to use high-order finite impulse response (FIR) filters, which increases the input-to-output delay and resource consumption of FPGA. To address this issue, a PC method with the infinite impulse response (IIR) filter is proposed in this brief. The design criteria of the IIR filter for PC is given. The FPGA implementation scheme and resource optimization are discussed. To verify the performance of the proposed method, MATLAB simulation and FPGA implementation are made with a 5G NR signal. The comparison with the state-of-the-art PC methods shows that the proposed technique can reduce the total time delay greatly, with good PC performance and low resource consumption.
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Peak Cancellation Method With IIR Filters
and Its FPGA Implementation
