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New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

( Click and Download this Project on Here ) ( Check Output Explanation Video file )

DOI: 10.1109/TCSII.2018.2878717

[/vc_column_text][vc_column_text] Abstract:

In this paper, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry look ahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best n-digit decimal adder design reduces the delay and area-delay product (ADP) by 50% compared with previous designs. We have implemented our designs using QCA Designer tool. The proposed QCA Designer based 8-digit PBA-BCD adder achieves over 38% less delay compared with the best existing designs.

Software Implementation:

• Xilinx 14.2

Advantages:

• Low power and high density.
• Low area, power and delay.
• Less hardware complicity.
• Utilization of majority gate is more

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