In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area is presented for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of these multiple output signals. A digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal to reduce the pulse width error and to make the duty cycle of each output signal approximately 50%. Designed using 0.18- μm CMOS technology, this DLL occupies an active area of 111.32 μm× 82.74 μm . With a 1.8 V supply voltage and a 250 MHz operating frequency, the measured power consumption and output phase error rate of this DLL are 2.28 mW and 1.3%, respectively.
Software Implementation:
Modelsim
Xilinx
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Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line
