In this brief, we propose a fully pipelined divider for single-precision floating-point numbers based on a universal piecewise linear (PWL) approximation method and a modified Goldschmidt algorithm. The state-of-the-art universal PWL method uses a suitable number of segments and fractional bit widths to meet the requirement of the predefined maximum absolute error. Small multipliers are employed in the modified Goldschmidt algorithm. In the hardware implementation, the multipliers are optimized with the radix-4 and radix-8 booth encoding methods to reduce the number of partial products. In addition, the sum of the partial products and other data are calculated by a compressor and an adder to shorten the critical path. Synthesized results show that the maximum achievable frequency of our design is better than those of the existing methods. In addition, our design shows overwhelming superiority in terms of latency and throughput compared with existing methods.
Software Implementation:
Modelsim
Xilinx
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High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers
