HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction
HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC NAND Flash Memory
Abstract:
Low-density parity-check (LDPC) codes have been widely adopted in 3-D NAND flash memory systems to enhance data storage reliability. However, when the raw bit error rate (RBER) during data read operations is high, the LDPC decoding process often incurs significant iterative latency, which severely impacts system performance. To address this challenge, this article introduces a novel heterogeneous feature mining for low-overhead latency reduction (HFMLLR) scheme. This scheme reconstructs data based on the distinct characteristics of LDPC codes and flash memory and then further leverages log-likelihood ratio (LLR) and interframe error properties to achieve an organic integration of these features. In detail, this scheme first systematically analyzes the divergent impact of information bits versus check bits on reliability within LDPC codes. By leveraging the inherent characteristic disparity between pages in 3-D TLC NAND flash, it proposes a disparity characteristic-based data reconstruction (DCDR) scheme. This approach naturally creates a reliability gradient within data frames without adding extra storage overhead. Furthermore, this article explores the mechanism by which the LLR influences decoding conver-gence. By taking advantage of the spatial correlation between multiframe errors within the same flash page, the HFMLLR scheme optimizes the decoding process, significantly reducing the number of iterations with minimal computational and storage overhead. Experimental results demonstrate that, compared to traditional schemes, the HFMLLR scheme achieves up to an 83.4% reduction in decoding iteration latency, highlighting its remarkable latency reduction capabilities and practical value.
” Thanks for Visit this project Pages – Register This Project and Buy soon with Novelty “
HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC NAND Flash Memory
