FPGA Implementation of a Real-Time Parallel Loop-Unrolled DFE
FPGA Implementation of a Real-Time Parallel Loop-Unrolled DFE for PAM-4 IM/DD Optical Links
Abstract:
This work presents a novel hardware-efficient FPGA implementation of a real-time parallel loop-unrolled decision feedback equalizer (DFE) for PAM-4 IM/DD optical links. The proposed DSP architecture integrates timing recovery, a 5-tap FFE, and a novel single-tap parallel DFE leveraging an 8 × 8 loop-unrolled structure and a hardware-friendly error-based tap update mechanism thus effectively reduces processing complexity and clock delay. The implementation occupies only 4.2% LUTs, 2.75% FFs, and 6.8% DSP48E2 resources of a Xilinx XCVU13P chip. A successful 29.4912 Gb/s real-time PAM-4 signal transmission over a 10 km SSMF is demonstrated using a cost-effective directly modulated laser (DML) and achieving a BER below the 7% HD-FEC threshold, indicating a scalable and efficient solution for high-speed short reach optical data links.
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FPGA Implementation of a Real-Time Parallel Loop-Unrolled DFE for PAM-4 IM/DD Optical Links
