DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations
DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations
Abstract:
An energy-efficient SRAM-based computing-in-memory architecture for general-purpose arithmetic operations is presented. The design introduces a diagonal-block parallel mapping scheme to improve hardware utilization and reduce vacant memory cells caused by irregular bit widths during computation. A hardware-efficient arithmetic flow with pipelined addition and shift-based multiplication and division reduces critical path delay and resource usage. Implemented using an 8T SRAM-CIM macro in 28-nm CMOS technology, the system achieves improved throughput and energy efficiency, reducing energy consumption and computing cycles by up to 55.9% and 60.9%, respectively, compared to conventional bit-parallel CIM architectures.
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DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations
