Balanced (3 + 2 log n)G Adders for Moduli Set {2n+1
, 2n + 2n−1 − 1, 2n+1 − 1}
[/vc_column_text][vc_column_text] Abstract:
Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set τ = {2n−1,2n, 2n + 1}, with nearly 23n dynamic range and fast parallel-prefix adders. However, the 2n + 1 channel is 4G slower (G = simple 2-input gate delay). To remedy such speed imbalance and accommodate higher dynamic ranges, other moduli forms have joined {2n, 2n−1}, with only slightly slower adders (e.g., 2n+1−1 (n = 2h),2n−2q−1(q < n − 1), and 2n−3, with at most 2G more parallel-prefix delay). However, the more the number of moduli, the harder and more costly becomes the required reverse convertor, while otherwise increasing the channel widths n may incur some speed loss. Nevertheless, in the present work, the 3-moduli set τ+ = {2n+1,2n+2n−1−1,2n+1−1} is presented, with almost 6× dynamic range than that of the aforementioned τ , where the corresponding parallel-prefix adders are as fast as those for the 2n and 2n−1 channels. The required nontrivial forward convertor for modulo 2n + 2n−1−1 and the reverse convertor for the new 3-moduli set are also designed. Moreover, a new 3-input parallel-prefix node is designed and incorporated, as appropriate for n = 2h, within the employed parallel-prefix networks with the overall advantage of 2G speed-up. Improvements of proposed designs are confirmed via circuit synthesis.
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Balanced (3 + 2 log n)G Adders for Moduli Set {2n+1
, 2n + 2n−1 − 1, 2n+1 − 1}
