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Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

DOI : 10.1109/TVLSI.2020.3008424

[/vc_column_text][vc_column_text] Abstract:

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, <; 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

 

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Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

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