Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance
Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges
Abstract:
Technology scaling and supply voltage reduction make sequential circuits around clock edges increasingly vul-nerable to single-event transients (SETs). This work analyzes the sensitive regions of a dual interlocked storage cell (DICE)-based flip-flop (DICEFF) in a 15 nm FinFET process and reveals the correlation between critical charge distribution and SET pulse characteristics. A lightweight fault-tolerant scheme is proposed that integrates delay elements (DEs) with the self-recovery capa-bility of DICE to temporally desynchronize SET pulse arrivals and facilitate self-correction through temporal misalignment. Furthermore, a visualization method based on critical charge distribution is presented to delineate SET tolerance boundaries. HSPICE simulations demonstrate that the proposed method is robust against PVT variations, improving the average critical charge by up to 1.7× over the baseline and reducing the risk window by 47%, while maintaining comparable delay and power efficiency.
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Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges
