N -path switching systems using switched-series R-C networks are analyzed in the context of RF receiver front-ends, and it is shown that it is possible to mitigate the need to generate an accurate low power clock at high frequencies by operating at higher order harmonics of the switching frequency. For values of N that are an integer factor of 4 (i.e., N = 4, 8, and 16), harmonic selection RF receivers’ architectures are presented using two feed-forward N -path switching filters and harmonic recombination at the baseband. Moreover, it is demonstrated how the harmonic recombination stage at the baseband can be reconfigured to select the third harmonic of the switching frequency rather than the fundamental to reduce the input frequency and power consumption of the multi-phase clock generator by a factor of 3. In addition, to analyze the performance of the proposed RF receiver architecture, multiple receivers have been designed and post-layout simulated in two CMOS technologies, TSMC 130 nm and TSMC 65 nm. The resulting 5.7–7.2-GHz RF receiver architectures allow for operation at the third harmonic of the LO frequency (i.e., 1.9–2.4 GHz), reducing power consumption and allowing for good performance metrics at both studied technology nodes.
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Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures
