An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems
An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems
Abstract:
To overcome the trilemma between application flexibility, high efficiency, and minimal area/power overhead in baseband processors, this article proposes an area-efficient and reconfigurable accelerator for massive multiple-input-multiple-output (MIMO) systems, integrating a reconfigurable and heterogeneous processing element (PE) array featur-ing customized mixed-precision floating-point units (FPUs) to enable high-accuracy execution of diverse baseband opera-tions (i.e., general matrix computation, inversion, mixed-radix fast fourier transform (FFT), decomposition, etc.) on matri-ces ranging from 4 × 4–32 × 32. Addressing challenges posed by irregular partitioning and unbalanced decomposi-tion in complex operations, an efficient heterogeneous mapping (EHeM) technology is introduced, achieving over 75% PE array utilization by minimizing external data access and reconfiguration overhead. Furthermore, a multibank memory structure with a dynamic access strategy (DAS) eliminates access conflicts and synchronizes memory-PE bandwidth across varying operators. This accelerator, validated on Xilinx Virtex-7 XC7VX690T, supports multiple baseband algorithms and signal processing operations, such as minimum mean square error (MMSE), FFT, and filtering. Evaluations show up to 75.41× throughput improvement and 239.30× efficiency improvement over operator-specific designs, and 1.10×–6.02× higher efficiency than prior works for full MIMO processing.
” Thanks for Visit this project Pages – Register This Project and Buy soon with Novelty “
An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems
