Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes
Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes
Abstract:
Wireless sensor network (WSN) has emerged as a significant application among Internet-of-Things (IoT) applications. Energy harvesting systems have a high potential for deployment in WSN to monitor natural environments and industrial equipment. With limited resources, including power and chip area, an energy harvesting system demands thorough resource allocation to several circuits like a control system, sensors, and a transceiver. Also, such systems are required to function with low-peak power to adapt to the fluctuation of harvested energy. This brief presents a System-on-Chip (SoC) featuring a tiny 16-bit processor for batteryless systems. The processor is implemented using an accumulator-based instruction set architecture, realizing a small-scale design. The SoC integrates the 16-bit processor, two static random-access-memory blocks (1KB and 512B) for instruction, and data memory and peripherals for communication. It is fabricated on general-purpose CMOS 180nm and Silicon On-Thin-Buried Oxide (SOTB) 65nm process. Implemented results show the total area cost of the SoC is 241, 036μm2 and 52, 558μm2 on CMOS 180nm and SOTB. The SoC design achieves low-peak power consumption at 0.6μW and on the CMOS 180nm chip. Power consumption can decline further with a key technique in varying the back body bias by SOTB technology to 21.56nW. The minimum energy point is observed to be 10.38μW /MHz and 0.64μW /MHz in CMOS 180nm and SOTB 65nm chips, respectively. The small-scale features in size and power dissipation make the proposed SoC suitable for energy harvesting applications.
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Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes
