A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures
A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures
Abstract:
Digital static random access memory-based in-memory computing (SRAM-IMC) is a promising computation paradigm to break the von-Neumann bottleneck. However, the IMC architectures also bring a series of challenges for testing, because of the circuit structures and operations that do not exist in the conventional memories. One of the challenges is the testing of evaluation circuits in the digital SRAM-IMC architectures, because the primary inputs (PIs) of the evaluation circuits cannot be directly accessed by the testers. Several test approaches such as the conventional logic built-in self-test (LBIST) modules, the indirect and the scan-chain-based test methods are proposed to address this issue. Nevertheless, these solutions suffer from the low test performance or the high area consumption. This work proposes a reconfigurable built-in self-test (BIST) scheme for the evaluation circuits. By reusing the IMC bitcells and operations, the proposed BIST scheme implements the separate pattern generation (PG) and response analysis (RA) processes. Furthermore, the diverse pattern generators, including the Fibonacci linear feedback shift register (LFSR) and weighted LFSR (WLFSR) with adjustable feedback polynomials and the cellular automata (CA), are realized to improve the test efficiency and fault coverage. The evaluation results show that the proposed BIST scheme has better test performance comparing with the indirect and the scan-chain-based test approaches. The proposed BIST scheme has comparable test performance, whereas it has much less area overhead comparing with the conventional LBIST schemes. Additionally, the proposed BIST scheme is testable and repairable.
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A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures
