Memory test using automatic test equipment (ATE) has been generally applied to improve memory yield. Memory test patterns are generated by algorithmic pattern generator (ALPG) within the ATE. To test the high-speed memory, parallel ALPG employing multiple pattern generators (PGs) has been proposed. However, this method has limitations due to restrictions in arithmetic operation for memory test pattern generation and considerable area requirements. Moreover, utilizing conventional instruction set architecture (ISA) to construct pipelined PG can be challenging to maximize the performance of the ALPG. To address these limitations, a new ISA for high-speed and area-efficient ALPG is proposed. The experimental results indicate that the parallel ALPG based on the proposed ISA can generate and transmit the test patterns to memory-under-test (MUT) at a higher speed than the conventional methods with the same number of PGs. In addition, higher area reduction can be achieved as the target test rate increases.
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