Time-to-digital converters (TDCs) based on field-programmable gate array (FPGA) generally use a tapped delay line (TDL) to propagate the hit signal for time interpolation within one system clock cycle. The length of TDL is normally required to provide the total delay time larger than one system clock period, and all taps of TDL are sampled for encoding, which causes unnecessary logic resource consumption. In this article, we propose to interpolate the system clock cycle with a folding TDL. The shorter TDL with fewer sampled taps can significantly save logic resource usage. We will also demonstrate that the multiedge measurement technique is still available to this folding TDC for precision improvement. In a Xilinx Kintex-7 FPGA, three pairs of such folding TDCs with folding factors of 2–4 are implemented and performance evaluated. The average rms precision is measured as 4.6, 5.6, and 6.4, respectively, over time intervals from 0 to 50 ns. Compared with the normal TDL-TDC with similar performance, the proposed folding TDC can save more than 50% of logic resources. This advantage makes the TDC helpful to applications requiring multiple TDC channels.
Software Implementation:
Modelsim
Xilinx
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A High-Precision Folding Time-to-Digital Converter Implemented in Kintex-7 FPGA
