This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The subrange SAR ADC architecture is applied to achieve 100-MS/s. A foreground offset tracking scheme is proposed to reduce the offset deviation between the coarse and fine ADCs. A simple binary-window DAC switching scheme is applied to maintain both the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The prototype SAR ADC was implemented using a 65-nm CMOS technology. At 100-MS/s, it consumed a total power of 1.9 mW from a 1.2 V supply. The measured differential nonlinearity and integral nonlinearity were -0.8/+1.6 LSB and -1.2/+1.2 LSB, respectively. The peak SNDR and SFDR were 61.5 dB and 81 dB, respectively. At the Nyquist rate, the measured effective number of bits was 9.8, which is equivalent to a figure-of-merit of 21.3 fJ/conversion-step.
