A frequency-drift-compensated phase-locked loop (PLL) with an LC voltage-controlled oscillator (VCO) is fabricated in TSMC 40-nm CMOS process. The proposed frequency drift compensator employs an analog-to-digital converter to monitor the control voltage of the PLL in background. The capacitor banks are adjusted to compensate for the frequency drift of the LC-VCO. The measured reference spur is -65.15 dBc. The measured best phase noise of this PLL is -108.32 and -130.26 dBc/Hz at the frequency offset of 1 and 10 MHz, respectively, among five chips. This chip occupies 0.223-mm2 active area. The power dissipation of this PLL is 6.32 mW from a 0.9-V supply voltage. The average temperature coefficient is 2.43 ppm/°C from 20 °C to 100 °C.
