A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS
[/vc_column_text][vc_column_text] Abstract:
This paper presents a low-power 12-bit 100-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC). Several techniques are developed to enhance the ADC performance. The non binary capacitor array with small digital-to-analog converter (DAC) capacitors (total 394 fF) allows for reducing DAC settling time and power consumption while maintaining extremely high hardware utilization. The proposed nonlinear capacitance correction method solves the nonlinear capacitance problems of the comparator when the small unit capacitor is used. The latch output glitch removal method ensures the speed and accuracy of the comparator at the low supply voltage. Furthermore, the proposed high-speed SAR logic and timing sequence improved SAR logic’s operating speed by 75% compared with traditional SAR logic. The prototype was fabricated using a 40-nm CMOS technology. At a 0.9-V supply and 100-MS/s sampling rate, the ADC achieves a signal-to-noise distortion ratio of 67.3 dB and consumes 2.6 mW, resulting in a figure of merit of 14.6 fJ/conversion-step. The ADC core occupies an active area of only 50 × 280 µm2.
