Hierarchical Approximate Min-Sum and Multi-Frame Parallel QC-LDPC
Hierarchical Approximate Min-Sum and Multi-Frame Parallel QC-LDPC Decoder for FPGA Optical Links
Abstract:
In this letter, we present an efficient quasi-cyclic low-density parity-check (QC-LDPC) decoder designed for resource-constrained satellite laser communication terminals. We propose a novel approximate min-sum algorithm that incor-porates node grouping and hierarchical comparison, reducing comparator and multiplexer (MUX) usage by 39% and 52%, respectively, with only a negligible 0.02 dB performance degrada-tion. To maximize hardware efficiency, we propose a multi-frame parallel architecture with asynchronous scheduling, achieving near-optimal 99.8% on-chip block RAM (BRAM) utilization and eliminating pipeline stalls. Experimental results demonstrate that the proposed decoder supports 2 Gbps binary phase-shift keying (BPSK) transmission with a minimum required received optical power (ROP) of –53 dBm.
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Hierarchical Approximate Min-Sum and Multi-Frame Parallel QC-LDPC Decoder for FPGA Optical Links
