A 1.5-GS/s 7-bit Charge-Injection SAR ADC Using a PVT-Tracking 1-bit Metastability Detector
A 1.5-GS/s 7-bit Charge-Injection SAR ADC Using a PVT-Tracking 1-bit Metastability Detector
Abstract:
This brief presents a 7-bit 1.5GS/s area-efficient asynchronous Charge Injection Successive Approximation Regis-ter (CI-SAR) analog-to-digital converter (ADC). The proposed ADC architecture consists of a 6-bit CI-SAR and a 1-bit Metastability Detector (MD), forming a 7-bit ADC. Superior area efficiency is achieved by architecting the CI-DAC in a segmented structure. The Charge Injection Cell (CIC) is biased by a temperature-aware bias generator that maintains the ADC full-scale over a wide temperature range. The gm -boosted strongARM comparator helps achieve high sampling speed up to 1.5GS/s. A background-calibrated metastability-detector extracts an addi-tional bit under different process, voltage, and temperature (PVT) conditions. The proposed ADC is fabricated in 28nm CMOS process in an area of 202µm2 . The peak SNDR is 39.04dB with FoMw = 17.4fJ/conv.-step. The measured SNDR drops by less than 2.7dB across the −40◦ C to 80◦ C temperature variation and 0.9V to 1.1V supply voltage variation.
” Thanks for Visit this project Pages – Register This Project and Buy soon with Novelty “
A 1.5-GS/s 7-bit Charge-Injection SAR ADC Using a PVT-Tracking 1-bit Metastability Detector
