FPGA Implementation of Highly Optimized Hybrid Approximate Multiplier using Approximate Parallel Prefix Adder

1. To developed the Parallel Prefix Adder of 8-bit, 12-bit and 16-bit using Accurate and Approximate method.
2. Approximation applied only the LSB of each parallel prefix adder.
3. To designed the 8×8 Hybrid PPA Approximate Multiplier and compared with PPA Hybrid Multiplier design.

Proposed Abstract:

This paper presents the FPGA implementation of a highly optimized Hybrid Approximate Multiplier designed using Approximate Parallel Prefix Adders (AxPPAs). The proposed design applies approximation selectively to the least significant bits (LSB) of hybrid adders, leveraging the strengths of Brent Kung and Kogge Stone architectures to balance accuracy, speed, and area efficiency. Experimental validation on an 8×8 multiplier reveals a 24.7% reduction in Slice LUTs, a 16.7% reduction in occupied slices, and an 11.8% decrease in delay, while maintaining the same power consumption as exact designs. These results highlight the design’s effectiveness in achieving significant improvements in computational performance and hardware efficiency. The implementation is particularly suited for error-resilient applications such as signal processing, machine learning, and image processing. This work demonstrates the potential of AxPPA-based designs for modern VLSI systems requiring energy-efficient, high-speed, and low-area solutions.

Software Implementation:

• Modelsim
• Xilinx

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A Novel Design of High Speed Multiplier Using Hybrid Adder Technique