Proposed Title :

FPGA Evaluation of four estimated Dadda multipliers for low-power applications

Improvement of this project :

• To develop the 8×8 Approximate Multiplier, which developed using four different architectures, and it given as,

• Almost Full adder, Full adder and Half adder – Conventional design

• 4:2 Compressor which developed with two Almost Full Adder

• 4:2 Compressor which developed with Almost Full Adder and Multiplexer

• 4:2 Compressor which developed with Majority Logic

• This work was developed with Verilog HDL, and synthesized this work in Xilinx Vertex-5 FPGA and compared all the parameters in terms of area, delay and power.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

Approximate computing is a commonly used technique for achieving energy-efficient system design in the field of Very Large-Scale Integration. This method is particularly well-suited for applications like signal processing and multimedia, since the primary focus is on minimizing power consumption. Approximate computing may provide faster and more substantial outcomes, although at the expense of less precision. In this study, we have presented innovative design methodologies that rely on a range of mono-lithic 4:2 compressors. The proposed methodology is used in order to minimize the number of steps involved in the process of partial product multiplication. The performance of the monolithic compressor has been seen to surpass that of several 4:2 compressors. The solution we proposed is based on the use of majority reasoning in conjunction with Dadda multiplication. This multiplier implements a novel partial product reduction format, resulting in a decrease in the maximum output delay. The consumption of logic sizes is greatly reduced by this strategy in comparison to other multipliers, such as Wallace Tree Multipliers. The simulation and synthesis results are compared with the standard Dadda multiplier with 4:2 compressors. The study included the synthesis of a proposed Dadda multiplier, which used approximation computing and majority logic, using a Xilinx Vertex-5 FPGA. The performance of this multiplier was then compared to existing compressors in terms of area usage, dynamic power reduction, and processing time.

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Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors