Distributed arithmetic (DA) is generally used for area-time efficient implementation of inner products, where one of the vectors is fixed and known a priori. Therefore, the conventional DA architectures cannot be used when both vectors are variable. This article proposes a novel architecture for computing inner products of variable vectors, where one of the vectors is encoded using the radix-4 modified Booth technique to reduce the logic complexity. The proposed structure for inner-product computation consists of two sections. The first Section of the architecture performs a carry-save reduction of the partial-inner-products of the same weight to two words. During every successive clock cycle, it reduces such partial-inner-products of different weights in the order of the lowest to the highest weight. In the second Section of the architecture, the pair of reduced words produced by the first Section are shift accumulated. The area, delay, and power saving are achieved by reducing the overall critical path of the structure as well as the logic complexity in both sections. The proposed architecture is synthesized by Cadence Genus using TSMC 90-nm technology library and place-and-route using Cadence Innova’s for different inner-product lengths and word lengths. The post layout synthesis results show that the proposed DA-based architecture offers significant advantages in area-delay product (ADP) and energy per computation (EPC) over the radix-4 Booth multiplier-accumulator-based architectures.
Software Implementation:
Xilinx
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Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors
