Proposed Title :

FPGA Implementation of Concurrent Multi Band Transmission to design at 8th Order Reconfigurable Digital Delta Sigma Modulation Transmitter Architecture

Improvement of this project :

• To design 4th Order Reconfigurable Multi Band Delta Sigma Modulation with using Truncated Multiplier instead of Conventional Multiplier.

• To design 8th Order Reconfigurable Multi Band Delta Sigma Modulation with using Truncated Multiplier instead of Conventional Multiplier.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

In contemporary wireless communication technology, the priority requirement for energy and spectrum efficient reconfigurable transmitter design with a high data rate has increased substantially, as a result conventional reconfigurable transmitter design will be inefficient throughout the amplification phases. The flexibility to reconfigurable transmitter design with carrier spacing and the quality of continuous carrier aggregation system is suggested in the long-term evolution advanced (LTE-A) standard for such high data rate transmission. In which this work present the huge bandwidth of carrier signal is split into multiple sub-carriers with lower bandwidth. These multi band transmission will more helpful in 5G application. This work describes 8th order reconfigurable multi-band delta sigma modulator (RMB – DSM), which allows the noise transfer function zero to be adjusted to fall at different frequencies where the carriers are aggregated. In the case of multi-band transmission, quantization noise between transmission bands is a major concern. As a result, a multi-band additional noise shaping (ANS) function is also implemented, which produces notches around each carrier and decreases noise levels across a number of pass-bands. The systematic architecture of the present 4th order reconfigurable multi-band delta sigma modulator will have increases logic size and energy consumption, and the arithmetic operations of the logic will need a large amount of logic in VLSI implementation. As a result, the proposed work would minimize the amount of logic size in arithmetic operations by utilizing an energy quality scalable truncated technique, which present with 8th order reconfigurable multi-band delta sigma modulator, these truncated technique will reduce the internal and external logic in RMB-DSM architecture, it will provide only n size output from the n x n multiplication. The proposed work for aggregating up to four 20 MHz long term evolution (LTE) signals with an overall aggregated bandwidth of 160 MHz with sampling frequency of 1 GHz has been conformed in simulation and experiment. This implementation of existing and proposed design will have implemented in Xilinx Zynq 7000 FPGA and proved the performance of logic size, delay and power.

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Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band Transmission