Proposed Title :

VLSI Implementation of Convolution /
Strided Convolution Checksum Checker using Reversible logic Gates for Deep
learning and Neural Networks

Improvement of this Project:

• The proposed work developed with ConvGuard method using reversible logic gates to reduce amount of power and logic size for the accumulation of the input pixels without the need for huge garbage logics.

• To design the Convolution Checksum Checker and Strided 2 Convolution Checksum Checker at 7×7 image matrix size and compare both using reversible logic.

Software implementation:

• Modelsim
• Xilinx

Proposed System:

In the method of random hardware defects, the faults need to be recognized on online in order to more accurately manage random hardware issues. This makes recovery much easier. It has been suggested that algorithm-based fault tolerance might be used as a low-cost technique to validate the results of computations online, against the possibility of random hardware failures. In this instance, a hardware checker compares the checksum of the actual result to a predicted checksum that was calculated in parallel by the checker. In this proposed work, our primary focus is on the creation of checkers for convolution engines, which are the fundamental component of image processing and digital applications at the present time. ConvGuard is the name given to the proposed convolution checksum checker that makes use of a recently developed invariance condition of convolution. ConvGuard taken the amount of power that is for the accumulation of the input pixels without the need for huge buffers to store the intermediate checksum findings. Thus, the proposed work developed with ConvGuard method using reversible logic gates to reduce amount of power and logic size for the accumulation of the input pixels without the need for huge garbage logics. The results of the experiments reveal that ConvGuard uses just a tiny proportion of the space and power of an effective convolution engine, while at the same time being substantially smaller and more power efficient than a state-of-the-art checksum checker for a variety of realistic applications. Finally, this work was built in Verilog HDL, synthesised on a Xilinx Vertex-5 FPGA, and all parameters in terms of area, delay, and power were compared.

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Low Cost Online Convolution Checksum Checker