A 2.4 GHz type-I phase-locked loop with foreground loop bandwidth calibration is presented. A successive approximation method is presented to calibrate the loop bandwidth by digitally adjusting the switch size of the master-slave sampling filter. This brief is fabricated in 45 nm CMOS technology. Its active area is 0.013 mm 2 . The power consumption is 3.6 mW at 2.4 GHz for a supply of 0.9 V. The integrated jitter over 1 kHz to 100 MHz is 3.6 ps. With the supply voltage of 0.88V~0.92V, the variation of the loop bandwidth is reduced from 18.7% to 4.6% by using the loop bandwidth calibration.
Software Implementation:
Modelsim
Xilinx
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A Type-I PLL With Foreground Loop Bandwidth Calibration
