Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions encounter the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with small and constant resource utilization. The experimental results show that the resource utilization of the proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than that of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has lower resource utilization, by 81.7%-85.9% and 2.9%-20.8%, than two state-of-the-art architectures. Furthermore, throughput and programmability are guaranteed. The source code has been made available on -1.5mm]Please cite reference [1] in the text of the paper. It was removed from the abstract as having references in an abstract is contrary to IEEE journal style. GitHub.
Software Implementation:
Modelsim
Xilinx
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Low-Cost and Programmable CRC Implementation Based on FPGA
